In the manufacture of integrated circuits on silicon, self-alignment between the gate and the source and drain regions has previously been used to improve FET device performance over prior structures in which the gate overlapped the source and drain regions. Conventionally, as shown in Millman, Microelectronics, pp. 250-252 (1979), self-alignment is obtained in MOSFET fabrication by first applying the gate metallization, masking to define implant regions on each side of the gate, and then ion implanting into silicon through openings in the mask on each side of the gate. The implanted ions cannot penetrate the gate metal and therefore the ions enter the substrate only through the mask openings on either side of the gate. Ion implantation is essentially a line-of-sight process and so the edges of the implant regions are closely aligned with the edges of the gate metallization.
Recently, substantial attention has been devoted to the fabricationn of FET circuits in gallium arsenide. In constructing a field effect device in a semiconductor material such as silicon, i.e., to make a MOSFET, the metal gate electrode is separated by an oxide layer from the semiconductor channel. In making field effect devices in a semi-insulating material, such as GaAs, the gate metal is placed in direct contact with the semiconductor. An example of one process for making GaAsFET digital integrated circuits is described in "A High-Yield GaAs MSI Digital IC Process" by A. Rode, A. McCamant, G. McCormack and B. Vetanen, published in the minutes of the International Electron Devices Meeting, December 1982. This article describes a depletion-mode non-self-aligned gate GaAsFET process.
In the case of a depletion-mode device, with the gate unbiased, the active region below the gate is conductive. However, for many applications, it is preferable for such region to be nonconductive when the gate is unbiased, which requires an enhancement-mode (E-mode) structure. In GaAsFET devices, enhancement-mode requires that the channel be lightly doped or thin enough that the inherent gate depletion layer pinches off the channel at zero gate bias.
It is also necessary, however, to maintain conductivity on either side of the channel, between the source and gate and between the gate and drain. In a device shown in FIG. 1 of the Rode, et al. article, the gate is spaced apart from both the source and drain regions. Sufficient conductivity is inherently provided on either side of the gate in depletion-mode devices. Reducing active region thickness, or doping concentration, to make an enchancement mode device, undesirably reduces conductivity alongside the gate, which undesirably increases resistance, particularly source resistance R.sub.s which also reduces device gain.
Two different enhancement-mode GaAsFET design approaches have been developed, which endeavor in different ways to maintain adequate active region conductivity alongside the gate, while obtaining enhancement-mode characteristics beneath the gate. One approach is to use a thin active layer, disposed close to the substrate surface beneath a planar gate, together with self-aligned implants on either side of the channel. The other approach is to use a deep active layer, together with a gate which is recessed into the substrate to provide a thin channel beneath the gate but thicker conductive regions on either side of the gate. Examples of these two design approaches are next described.
An early self-aligned GaAsFET gate process is described in an article entitled "EB-Writing N+ Self-Aligned GaAs MESFETs for High-Speed LSIs," International Electron Devices Meeting, December 1982, by K. Yamasaki, N. Kato, Y. Matsuoka, and K. Ohwada and in "Self-Align Implantation for N.sup.+ -Layer Technology (SAINT) for High-Speed GaAs Ics," Electron. Lett. V. 18, pp. 119-121, February 1982, by K. Yamasaki, K. Asai, T. Mizutani, and K. Kurumada. The described SAINT process is intended to produce very high-speed GaAsFETs by reducing gate length. In this process, a multi-layer self-aligned implant mask is applied to a semi-insulating GaAs substrate, upon which a silicon nitride passivation film has been deposited. The bottom mask layer is selectively etched to undercut the mask. After N+ implantation, a layer of SiO.sub.2 is applied, the mask is removed, the silicon nitride film is plasma etched to expose the substrate, and the gate metal is applied. The foregoing procedure produces a planar self-aligned gate contact which has a length in contact with the substrate that is defined by the edges of the SiO.sub.2 layer and is spaced inward of the N+ implants. Unfortunately, use of a planar gate forfeits the ability to manipulate the physical thickness of the active layer. Only dopant concentration and doping depth of the active layer remain for manipulation to regulate enhancement-mode device characteristics.
Alternatively to the planar self-aligned gate configuration described above, it has been proposed to form a recess in the substrate to receive the gate metallization. For example, a recessed gate has been incorporated into the non-aligned GaAsFET structure disclosed in the foregoing article by Rode, et al. This approach has certain advantages over a planar gate contact, particularly in controlling the effective thickness of the active layer of the device. The depth of the recess can be manipulated, in addition to doping concentration and overall depth of the active region, to control enhancement-mode characteristics of the device. Use of a recessed gate also allows the active region to be made relatively thick alongside the gate to maintain conductivity and to minimize surface depletion effects which can reduce device gain.
Difficulties arise, however, in accurately positioning the recess, which must be formed prior to applying the gate. In particular, it is difficult to position the recess and gate consistently relative to the source and drain regions. Consequently, use of a recessed gate has not found wide acceptance. The 1984 Technical Digest of the IEEE GaAs IC Symposium reports the current state of the gallium arsenide integrated circuit art. In the area of circuit fabrication, articles entitled "A Self-Aligned Gate Modulation-Doped (Al,Ga)As/GaAs FET IC Process," by N. C. Cirillo, Jr., J. K. Abrokwah, and S. A. Jamison (pp. 167-170) and "A Low Power Gigabit IC Fabrication Technology," M. J. Helix, S. A. Hanka, P. J. Vold, and S. A. Jamison (pp. 163-166) both reject the use of recessed gate designs in favor of planar gate designs in making self-aligned gate enhancement-mode GaAs MESFETs and MODFETs.
Another problem arises in annealing self-aligned GaAsFETs after gate deposition. Furnace annealing is conventionally carried out over, e.g., 20 minutes, at about 800.degree. C. At such high temperatures a difference in coefficients of thermal expansion produces stresses at the interface between the metal gate and gallium arsenide, causing inferior Schottky barrier properties. Migration of impurities from the gate metallization into the channel region during annealing also degrades device performance, as does lateral diffusion of the implanted silicon ions. These problems contribute to very low yields of operative GaAs devices. In the process described in the above-mentioned paper by Cirillo, et al., the researchers try to minimize these problems by using a rapid thermal anneal to activate the self-aligned gate implants instead of conventional furnace annealing. This manner of annealing appears from the report of Cirillo, et al. to offer satisfactory results but does not totally avoid heating, for a short time, of the Schottky interface. Metal can diffuse very rapidly at annealing temperatures. It remains to be seen whether rapid annealing such self-aligned devices will prove acceptable in production process. In view of the current lack of understanding of the physics of the Schottky interface, it would be preferable not to risk degradation of the gate by metal diffusion. The SAINT process, reported above by K. Yamasaki, et al., avoids such risk and seeks to controllably separate the N+ self-aligned implants from the planar gate contact by a distance equal to the expected lateral diffusion of the N+ implants. Known recessed gate designs likewise apply gate metalization after annealing.
Another limitation of prior self-aligned gate processes is that the implants on each side of the gate are essentially identical in dopant concentration. On one hand, it is preferable to have a high doping concentration between the source and gate to minimize source resistance R.sub.s. On the other hand, it is preferable to have a low doping concentration in the drain side implant to minimize gate/drain capacitance C.sub.GD. In conventional self-aligned gate processes, however, it is impractical to provide asymmetrical implant doping concentrations. In the SAINT devices described above, spacing the gate contact inward of the self-aligned N+ implants improves drain capacitance but degrades source resistance. In recessed gate devices, the difficulty of consistently positioning the recessed gate relative to the gate and drain implants makes these parameters highly variable, contributing to low device yield. It would be preferable for gate position to be noncritical.
Finally, it is well recognized as desirable to minimize gate dimensions, but the ability to minimize gate length is limited by difficulties in photolithographically reproducing small (e.g., submicron) features in photoresist. Also, the use of a very small dimension gate metallization produces a high gate metal resistance, R.sub.in. Smaller gate lengths also make it more difficult reliably to transfer small features from the photoresist into the wafer. For example, in the aforementioned SAINT process, it is difficult to control actual gate dimensions. The edges of the SiO.sub.2 layer are wedge-shaped because they are not deposited in a direct line of sight from the sputtering source. For the same reason, the structural integrity of the edges is poor. The edge of the SiO.sub.2 also is etched back by plasma. Consequently, the resulting gate is longer than the undercut mask and edge definition is poor.
Accordingly, a need remains for an improved self-aligned gate structure and process for fabricating self-aligned gates and to facilitate further reductions in gate length.